Phase-locked loop (PLL) systems are used extensively in analog and digital circuits. These systems typically include a phase frequency detector (PFD), charge pump and voltage controlled oscillator (VCO) connected in a feedback configuration. The VCO produces the output signal of the PLL, and the various components of the PLL cooperate to cause the output signal to tend toward and eventually lock on to a desired output frequency and/or phase, which are based on a reference signal applied as an input to the PFD. For example, many PLL systems are configured to produce an output signal having the same frequency as the input signal, or having an output frequency which is a factor x/y of the input frequency.
The output signal tracks the desired output frequency and/or phase through operation of a feedback mechanism, in which the output of the VCO is fed back to the PFD as a feedback signal via a feedback path. The phase frequency detector receives the reference signal and the feedback signal, and produces an error signal based on discrepancies between the actual phase and frequency of the output signal and the desired phase and frequency. The error signals from the PFD are applied to the charge pump, which in turn produces signals that control the oscillation frequency of the VCO.
A design consideration that can be important in PLL systems is the behavior of the PLL during startup or at other times when there is a significant difference between the actual phase/frequency of the output signal and its desired value. During normal operation, it is often desirable to operate the PLL at a relatively low bandwidth, in order to maintain lock and minimize tracking jitter. However, low bandwidth operation can significantly slow the locking process during startup or other times when a large adjustment in the output signal is desired. Prior systems have addressed this by temporarily elevating the bandwidth of the PLL in order to make a rapid initial adjustment to the output signal. However, many prior system suffer from disadvantages related to the timing at which they switch back into their normal lower-bandwidth state of operation. Commonly, this timing is determined in advance based on rough estimates of how the PLL will perform in a given operational setting. Typically, the timing is conservative and the transition to low bandwidth operation occurs sooner than necessary, because many PLL circuits cannot tolerate the overshoot and other potential consequences of a late transition to low bandwidth operation. Accordingly, many prior systems take longer than necessary to achieve lock during startup and other situations where relatively large corrections to the output signal are needed.